d-Matrix
Digital in-memory-compute (DIMC) chiplets built for fast, efficient inference
d-Matrix designs the Corsair inference accelerator using digital in-memory computing (DIMC) and chiplets to attack the memory-bandwidth bottleneck that limits GPU inference efficiency. Its architecture targets low-latency, high-throughput serving of large models at lower power than GPUs, and it raised a $110M+ Series B (Microsoft's venture arm among backers) with Corsair shipping toward 2025-2026. It competes in the inference-accelerator wave alongside Groq, Cerebras, and Etched.
Product
Corsair (DIMC chiplet inference)
Edge
In-memory compute vs HBM bandwidth wall
Backers
M12 (Microsoft), others
How it fits the stack
d-Matrix with what it depends on (above) and what it feeds (below). The figure renders as a crawlable diagram and upgrades to an interactive 3D graph as it scrolls into view.
d-Matrix in the AI stack. d-Matrix with its immediate upstream dependencies (top) and downstream dependents (bottom) in the AI value chain. Hover a node in 3D, or read the full relationships below.
Graph data (text) — 2 entities, 1 relationships
- d-Matrix —competes with→ Nvidia
Context — capital, rivals, policy · · 1