PCIe / CXL
Host bus and memory-coherent expansion fabric
PCIe (Gen5/Gen6) remains the host-to-accelerator bus, and CXL (Compute Express Link) adds cache-coherent memory pooling and expansion increasingly used to attack the HBM capacity wall in inference. Both are governed by industry consortia and gate how much memory and bandwidth a server node can address around each GPU.
Latest
PCIe 6.0, CXL 3.x
Use
memory pooling/expansion
How it fits the stack
PCIe / CXL with what it depends on (above) and what it feeds (below). The figure renders as a crawlable diagram and upgrades to an interactive 3D graph as it scrolls into view.
PCIe / CXL in the AI stack. PCIe / CXL with its immediate upstream dependencies (top) and downstream dependents (bottom) in the AI value chain. Hover a node in 3D, or read the full relationships below.
Graph data (text) — 3 entities, 2 relationships
- PCIe / CXL —used by→ Retimers & connectivity silicon (Astera, Credo)
- Nvidia Data-Center GPU (Blackwell/Rubin) —depends on→ PCIe / CXL
Depends on ↑ · 1