SMIC N+2 (7nm-class, DUV)
China's leading-edge node built without EUV — the hard ceiling
SMIC's N+2 process delivers 7nm-class chips (used for Huawei Ascend and Kirin) using multi-patterned DUV rather than banned EUV, at low yield and high cost. It is the practical ceiling of China's domestic leading-edge logic; pushing to 5nm-class without EUV faces severe yield and economic limits, making this the central hardware chokepoint for Chinese AI silicon.
Method
DUV multi-patterning (no EUV)
Use
Ascend, Kirin
How it fits the stack
SMIC N+2 (7nm-class, DUV) with what it depends on (above) and what it feeds (below). The figure renders as a crawlable diagram and upgrades to an interactive 3D graph as it scrolls into view.
SMIC N+2 (7nm-class, DUV) in the AI stack. SMIC N+2 (7nm-class, DUV) with its immediate upstream dependencies (top) and downstream dependents (bottom) in the AI value chain. Hover a node in 3D, or read the full relationships below.
Graph data (text) — 3 entities, 2 relationships
- Huawei Ascend (910B/910C) —depends on→ SMIC N+2 (7nm-class, DUV)
- SMIC (Semiconductor Manufacturing International Corp) —uses→ SMIC N+2 (7nm-class, DUV)