UCIe (chiplet interconnect)
Open die-to-die chiplet standard
UCIe (Universal Chiplet Interconnect Express) is the open die-to-die interconnect standard enabling multi-chiplet AI accelerators from mixed vendors, backed by TSMC, Intel, AMD, Arm, NVIDIA and others. As monolithic dies hit reticle limits, chiplet disaggregation over UCIe becomes the scaling path for AI silicon.
Type
Die-to-die interconnect
Backers
TSMC, Intel, AMD, Arm
How it fits the stack
UCIe (chiplet interconnect) with what it depends on (above) and what it feeds (below). The figure renders as a crawlable diagram and upgrades to an interactive 3D graph as it scrolls into view.
UCIe (chiplet interconnect) in the AI stack. UCIe (chiplet interconnect) with its immediate upstream dependencies (top) and downstream dependents (bottom) in the AI value chain. Hover a node in 3D, or read the full relationships below.
Graph data (text) — 3 entities, 2 relationships
- Nvidia Data-Center GPU (Blackwell/Rubin) —uses→ UCIe (chiplet interconnect)
- UCIe (chiplet interconnect) —partners with→ TSMC 3DFabric / InFO
Context — capital, rivals, policy · · 1