TSMC SoIC (System-on-Integrated-Chips)
3D chip-stacking (hybrid bonding) for next-gen accelerators
SoIC is TSMC's 3D die-stacking technology using bumpless hybrid bonding to vertically integrate multiple dies at very high interconnect density, often combined with CoWoS in a 3D+2.5D flow. It underpins next-generation compute tiles (e.g., AMD's stacked 3D V-Cache lineage and future Nvidia/AMD accelerator designs) and is a growing complement to CoWoS as chiplet architectures scale. Capacity and hybrid-bonding throughput make it another emerging packaging constraint for 2025-2026 flagship parts.
Function
3D hybrid-bonded die stacking (bumpless)
Pairing
Combined with CoWoS in 3D+2.5D flows
Users
AMD (3D V-Cache), future Nvidia/AMD parts
How it fits the stack
TSMC SoIC (System-on-Integrated-Chips) with what it depends on (above) and what it feeds (below). The figure renders as a crawlable diagram and upgrades to an interactive 3D graph as it scrolls into view.
TSMC SoIC (System-on-Integrated-Chips) in the AI stack. TSMC SoIC (System-on-Integrated-Chips) with its immediate upstream dependencies (top) and downstream dependents (bottom) in the AI value chain. Hover a node in 3D, or read the full relationships below.
Graph data (text) — 6 entities, 5 relationships
- TSMC SoIC (System-on-Integrated-Chips) —depends on→ BE Semiconductor (Besi)
- AMD —uses→ TSMC SoIC (System-on-Integrated-Chips)
- TSMC 3DFabric / InFO —uses→ TSMC SoIC (System-on-Integrated-Chips)
- TSMC SoIC (System-on-Integrated-Chips) —partners with→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- TSMC SoIC (System-on-Integrated-Chips) —designs→ TSMC (Taiwan Semiconductor Manufacturing Company)