TSMC CoWoS (Chip-on-Wafer-on-Substrate)
The advanced-packaging chokepoint gating AI GPU supply
CoWoS is TSMC's 2.5D advanced-packaging platform that co-integrates GPU/ASIC logic dies with stacks of HBM memory on a silicon interposer, and it is the single biggest packaging bottleneck for AI accelerators. Nvidia Blackwell/Rubin, AMD Instinct, and most HBM-bearing accelerators require CoWoS (variants CoWoS-S/R/L), making its capacity the practical ceiling on AI GPU shipments. TSMC has been aggressively multiplying CoWoS capacity through 2025-2026 (new AP fabs in Chiayi and Taichung) yet demand still outstrips supply.
Function
2.5D interposer co-packaging logic + HBM
Variants
CoWoS-S / CoWoS-R / CoWoS-L
Constraint
Capacity is the ceiling on AI GPU shipments
Users
Nvidia, AMD, Broadcom, Google TPU
How it fits the stack
TSMC CoWoS (Chip-on-Wafer-on-Substrate) with what it depends on (above) and what it feeds (below). The figure renders as a crawlable diagram and upgrades to an interactive 3D graph as it scrolls into view.
TSMC CoWoS (Chip-on-Wafer-on-Substrate) in the AI stack. TSMC CoWoS (Chip-on-Wafer-on-Substrate) with its immediate upstream dependencies (top) and downstream dependents (bottom) in the AI value chain. Hover a node in 3D, or read the full relationships below.
Graph data (text) — 17 entities, 18 relationships
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —depends on→ BE Semiconductor (Besi)
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —depends on→ DISCO Corporation
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —supplies→ DISCO Corporation
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —uses→ High-Bandwidth Memory (HBM)
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —uses→ Ibiden
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —supplies→ Resonac (CMP slurry & packaging materials)
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —supplies→ Shinko Electric
- AMD —depends on→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- Broadcom —uses→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- High-Bandwidth Memory (HBM) —uses→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- Hyperscaler Custom-ASIC Shift —depends on→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- Nvidia —depends on→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- Nvidia Data-Center GPU (Blackwell/Rubin) —uses→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- TSMC 3DFabric / InFO —uses→ TSMC CoWoS (Chip-on-Wafer-on-Substrate)
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —partners with→ ASE Technology (ASE Group / SPIL)
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —competes with→ JCET (advanced packaging)
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —competes with→ Panel-level / glass-substrate packaging
- TSMC CoWoS (Chip-on-Wafer-on-Substrate) —partners with→ TSMC SoIC (System-on-Integrated-Chips)
Depends on ↑ · 15
Feeds ↓ · 7
Context — capital, rivals, policy · · 6